In applications involving Application Specific Integrated Circuits (ASICs), embedded RAMs are often included for the temporary storage of data. In many applications, it is desirable that these RAMs have the ability to perform a read and a write every clock cycle. This capability is often provided by using a 2-port RAM (also called a dual-port RAM) with one port dedicated to the read operation and the second port dedicated to the write operation. The 2-port RAM has two sets of addresses, data in, data out, and read/write control signals each accessing the same set of 2-port memory cells.
The cost of an ASIC is generally, directly related to its area. Small chip size translates to lower manufacturing cost. However, the ever increasing complexity of operations being performed by ASICs tend to require more and more bits of memory storage, driving up the chip area. Therefore, it is important that the memory cell area be as small as possible to meet the need for increasing RAM bit counts.
A 2-port memory cell is considerably larger than a 1-port memory cell as it may include eight transistors, four bitlines and two wordlines (also referred to as rowlines) as compared to the six transistors, two bitlines, and one wordline often used in the 1-port memory cell. FIG. 1 illustrates the circuit schematics of traditional 1-port and 2-port static memory cells. The 1-port RAM can perform only one read or one write function every clock cycle. The 2-port RAM, although it can perform a read and a write every clock cycle, requires more circuitry to perform the read and write operations and to control the coordination of read and write access to the memory cell. This has a negative effect on the silicon area and therefore the cost of the ASIC. It would be advantageous in the art for a RAM that provides 2-port RAM functionality while using fewer components and taking up less space than the conventional 2-port RAM.